TDES1 contains the buffer sizes and other bits which control the descriptor chain/ring and the
Only
T-chip
frame being transferred.
Table 41-8 Transmit Descriptor 1
Bit
Description
31
IC: Interrupt on Completion
When set, this bit sets Transmit Interrupt (Register 5[0]) after the present frame has been transmitted.
30
LS: Last Segment
When set, this bit indicates that the buffer contains the last segment of the frame.
29
FS: First Segment
When set, this bit indicates that the buffer contains the first segment of a frame.
28:27
CIC: Checksum Insertion Control
These bits control the insertion of checksums in Ethernet frames that encapsulate TCP, UDP, or ICMP over IPv4 or IPv6 as described below.
2'b00: Do nothing. Checksum Engine is bypassed
2'b01: Insert IPv4 header checksum. Use this value to insert IPv4 header checksum when the frame encapsulates an IPv4 datagram.
2'b10: Insert TCP/UDP/ICMP checksum. The checksum is calculated over the TCP, UDP, or ICMP segment only and the TCP, UDP, or ICMP pseudo-header checksum is assumed to be present in the corresponding input frame’s Checksum field. An IPv4 header checksum is also inserted if the encapsulated datagram conforms to IPv4.
2'b11: Insert a TCP/UDP/ICMP checksum that is fully calculated in this engine. In other words, the TCP, UDP, or ICMP pseudo-header is included in the checksum calculation, and the input frame’s corresponding Checksum field has an all-zero value. An IPv4 Header checksum is also inserted if the encapsulated datagram conforms to IPv4.
The Checksum engine detects whether the TCP, UDP, or ICMP segment is encapsulated in IPv4 or IPv6 and processes its data accordingly.
26
DC: Disable CRC
When set, the GMAC does not append the Cyclic Redundancy Check (CRC) to the end of the transmitted frame. This is valid only when the first segment (TDES1[29]).
25
TER: Transmit End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor. The returns to the base address of the list, creating a descriptor ring.
24
TCH: Second Address Chained
When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather than the second buffer address. When TDES1[24] is set, TBS2 (TDES1[21–11]) are “don’t care” values.
TDES1[25] takes precedence over TDES1[24].
23
DP: Disable Padding
When set, the GMAC does not automatically add padding to a frame shorter than 64 bytes. When this bit is reset, the DMA automatically adds padding and CRC to a frame shorter than 64 bytes and the CRC field is added despite the state of the DC
(TDES1[26]) bit. This is valid only when the first segment (TDES1[29]) is set.
22
Reserved.
21:11
TBS2: Transmit Buffer 2 Size
These bits indicate the Second Data Buffer in bytes. This field is not valid if TDES1[24] is set.
10:0
TBS1: Transmit Buffer 1 Size
These bits indicate the First Data Buffer byte size. If this field is 0, the DMA ignores
this buffer and uses Buffer 2 or next descriptor depending on the value of TCH (Bit 24).
