Only
The descriptor addresses must be aligned to the bus width used (64). Each descriptor is provided with two buffers, two byte-count buffers, and two address pointers, which enable the adapter port to be compatible with various types of memory-management schemes.
Transmit Descriptor 0 (TDES0)
TDES0 contains the transmitted frame status and the descriptor ownership information.
T-chip
Table 41-7 Transmit Descriptor 0
Bit
Description
31
OWN: Own Bit
When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, this bit indicates that the descriptor is owned by the Host. The DMA clears this bit either when it completes the frame
transmission or when the buffers allocated in the descriptor are empty. The ownership bit of the First Descriptor of the frame should be set after all subsequent descriptors belonging to the same frame have been
set. This avoids a possible race condition between fetching a descriptor and the driver setting an ownership bit.
30:17
Reserved.
16
IHE: IP Header Error
When set, this bit indicates that the Checksum Offload engine detected an IP header error and consequently did not modify the transmitted frame for any checksum
insertion.
15
ES: Error Summary
Indicates the logical OR of the following bits:
JT: Jabber Timeout
When set, this bit indicates the GMAC transmitter has experienced a jabber time-out.
13
FF: Frame Flushed
When set, this bit indicates that the DMA/MTL flushed the frame due to a SW flush command given by the CPU.
12
PCE: Payload Checksum Error
This bit, when set, indicates that the Checksum Offload engine had a failure and did not insert any checksum into the encapsulated TCP, UDP, or ICMP payload. This failure can be either due to insufficient bytes, as
indicated by the IP Header’s Payload Length field, or the MTL starting to forward the frame to the MAC transmitter in Store-and-Forward mode without the checksum having been calculated yet. This second error
condition only occurs when the Transmit FIFO depth is less than the length of the
Ethernet frame being transmitted: to avoid deadlock, the MTL starts forwarding the frame when the FIFO is full, even in Store-and-Forward mode.
11
LC: Loss of Carrier
When set, this bit indicates that Loss of Carrier occurred during frame transmission.
This is valid only for the frames transmitted without collision and when the GMAC operates in Half-Duplex Mode.
10
NC: No Carrier
When set, this bit indicates that the carrier sense signal form the PHY was not asserted during transmission.
9
LC: Late Collision
When set, this bit indicates that frame transmission was aborted due to a collision occurring after the collision window (64 byte times including Preamble in RMII Mode and 512 byte times including Preamble and Carrier Extension in RGMII Mode). Not
valid if Underflow Error is set.
8
EC: Excessive Collision
When set, this bit indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. If the DR (Disable Retry) bit
in the GMAC Configuration Register is set, this bit is set after the first collision and the transmission of the frame is aborted.
7
VF: VLAN Frame
When set, this bit indicates that the transmitted frame was a VLAN-type frame.
6:3
CC: Collision Count
This 4-bit counter value indicates the number of collisions occurring before the frame was transmitted. The count is not valid when the Excessive Collisions bit (TDES0[8])
is set.
2
ED: Excessive Deferral
When set, this bit indicates that the transmission has ended because of excessive deferral of over 24,288 bit times (155,680 bits times in 1000-Mbps mode) if the
Deferral Check (DC) bit is set high in the GMAC Control Register.
1
UF: Underflow Error
When set, this bit indicates that the GMAC aborted the frame because data arrived late from the Host memory. Underflow Error indicates that the DMA encountered an empty Transmit Buffer while transmitting the
frame. The transmission process enters the suspended state and sets both Transmit
Underflow (Register GMAC_STATUS[5]) and Transmit Interrupt (Register GMAC_STATUS [0]).
0
DB: Deferred Bit
When set, this bit indicates that the GMAC defers before transmission because of the presence of carrier. This bit is valid only in Half-Duplex mode.
