Chapter 41 gmac ethernet Interface
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- T-chip Register description
MAC Management CountersThe counters in the MAC Management Counters (MMC) module can be viewed as an extension of the register address space of the CSR module. The MMC module maintains a set of registers for gathering statistics on the received and transmitted frames. These include a control register for controlling the behavior of the registers, two 32-bit registers containing interrupts generated (receive and transmit), and two 32-bit registers containing masks for the Interrupt register (receive and transmit). These registers are accessible from the Application through the MAC Control Interface (MCI). Non-32-bit accesses are allowed as long as the address is word-aligned. Only The organization of these registers is shown in Register Description. The MMCs are accessed using transactions, in the same way the CSR address space is accessed. The Register Description in this chapter describe the various counters and list the address for each of the statistics counters. This address will be used for Read/Write accesses to the desired transmit/receive counter. The MMC module gathers statistics on encapsulated IPv4, IPv6, TCP, UDP, or ICMP payloads in received Ethernet frames.
|
|
Name |
Offset |
Size |
Reset Value |
Description |
|
GMAC_MAC_CONF |
0x0000 |
W |
0x00000000 |
MAC Configuration Register |
|
GMAC_MAC_FRM_FI LT |
0x0004 |
W |
0x00000000 |
MAC Frame Filter |
|
GMAC_HASH_TAB_H I |
0x0008 |
W |
0x00000000 |
Hash Table High Register |
|
GMAC_HASH_TAB_L O |
0x000c |
W |
0x00000000 |
Hash Table Low Register |
|
GMAC_GMII_ADDR |
0x0010 |
W |
0x00000000 |
GMII Address Register |
|
GMAC_GMII_DATA |
0x0014 |
W |
0x00000000 |
GMII Data Register |
|
GMAC_FLOW_CTRL |
0x0018 |
W |
0x00000000 |
Flow Control Register |
|
GMAC_VLAN_TAG |
0x001c |
W |
0x00000000 |
VLAN Tag Register |
|
GMAC_DEBUG |
0x0024 |
W |
0x00000000 |
Debug register |
|
GMAC_PMT_CTRL_S TA |
0x002c |
W |
0x00000000 |
PMT Control and Status Register |
Only
T-chip
|
Name |
Offset |
Size |
Reset Value |
Description |
|
GMAC_INT_STATUS |
0x0038 |
W |
0x00000000 |
Interrupt Status Register |
|
GMAC_INT_MASK |
0x003c |
W |
0x00000000 |
Interrupt Mask Register |
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GMAC_MAC_ADDR0_ HI |
0x0040 |
W |
0x0000ffff |
MAC Address0 High Register |
|
GMAC_MAC_ADDR0_ LO |
0x0044 |
W |
0xffffffff |
MAC Address0 Low Register |
|
GMAC_AN_CTRL |
0x00c0 |
W |
0x00000000 |
AN Control Register |
|
GMAC_AN_STATUS |
0x00c4 |
W |
0x00000008 |
AN Status Register |
|
GMAC_AN_ADV |
0x00c8 |
W |
0x000001e0 |
Auto_Negotiation Advertisement Register |
|
GMAC_AN_LINK_PAR T_AB |
0x00cc |
W |
0x00000000 |
Auto_Negotiation Link Partner Ability Register |
|
GMAC_AN_EXP |
0x00d0 |
W |
0x00000000 |
Auto_Negotiation Expansion Register |
|
GMAC_INTF_MODE_ STA |
0x00d8 |
W |
0x00000000 |
RGMII Status Register |
|
GMAC_MMC_CTRL |
0x0100 |
W |
0x00000000 |
MMC Control Register |
|
GMAC_MMC_RX_INT R |
0x0104 |
W |
0x00000000 |
MMC Receive Interrupt Register |
|
GMAC_MMC_TX_INT R |
0x0108 |
W |
0x00000000 |
MMC Transmit Interrupt Register |
|
GMAC_MMC_RX_INT _MSK |
0x010c |
W |
0x00000000 |
MMC Receive Interrupt Mask Register |
|
GMAC_MMC_TX_INT _MSK |
0x0110 |
W |
0x00000000 |
MMC Transmit Interrupt Mask Register |
|
GMAC_MMC_TXOCTE TCNT_GB |
0x0114 |
W |
0x00000000 |
MMC TX OCTET Good and Bad Counter |
|
GMAC_MMC_TXFRMC NT_GB |
0x0118 |
W |
0x00000000 |
MMC TX Frame Good and Bad Counter |
|
GMAC_MMC_TXUND FLWERR |
0x0148 |
W |
0x00000000 |
MMC TX Underflow Error |
|
GMAC_MMC_TXCARE RR |
0x0160 |
W |
0x00000000 |
MMC TX Carrier Error |
|
GMAC_MMC_TXOCTE TCNT_G |
0x0164 |
W |
0x00000000 |
MMC TX OCTET Good Counter |
|
GMAC_MMC_TXFRMC NT_G |
0x0168 |
W |
0x00000000 |
MMC TX Frame Good Counter |
|
GMAC_MMC_RXFRM CNT_GB |
0x0180 |
W |
0x00000000 |
MMC RX Frame Good and Bad Counter |
|
GMAC_MMC_RXOCTE TCNT_GB |
0x0184 |
W |
0x00000000 |
MMC RX OCTET Good and Bad Counter |
|
GMAC_MMC_RXOCTE TCNT_G |
0x0188 |
W |
0x00000000 |
MMC RX OCTET Good Counter |
Only
T-chip
|
Name |
Offset |
Size |
Reset Value |
Description |
|
GMAC_MMC_RXMCF RMCNT_G |
0x0190 |
W |
0x00000000 |
MMC RX Mulitcast Frame Good Counter |
|
GMAC_MMC_RXCRCE RR |
0x0194 |
W |
0x00000000 |
MMC RX Carrier |
|
GMAC_MMC_RXLENE RR |
0x01c8 |
W |
0x00000000 |
MMC RX Length Error |
|
GMAC_MMC_RXFIFO OVRFLW |
0x01d4 |
W |
0x00000000 |
MMC RX FIFO Overflow |
|
GMAC_MMC_IPC_IN T_MSK |
0x0200
|
W
|
0x00000000 |
MMC Receive Checksum Offload Interrupt Mask Register |
|
GMAC_MMC_IPC_IN TR |
0x0208 |
W |
0x00000000 |
MMC Receive Checksum Offload Interrupt Register |
|
GMAC_MMC_RXIPV4 GFRM |
0x0210 |
W |
0x00000000 |
MMC RX IPV4 Good Frame |
|
GMAC_MMC_RXIPV4 HDERRFRM |
0x0214 |
W |
0x00000000 |
MMC RX IPV4 Head Error Frame |
|
GMAC_MMC_RXIPV6 GFRM |
0x0224 |
W |
0x00000000 |
MMC RX IPV6 Good Frame |
|
GMAC_MMC_RXIPV6 HDERRFRM |
0x0228 |
W |
0x00000000 |
MMC RX IPV6 Head Error Frame |
|
GMAC_MMC_RXUDPE RRFRM |
0x0234 |
W |
0x00000000 |
MMC RX UDP Error Frame |
|
GMAC_MMC_RXTCPE RRFRM |
0x023c |
W |
0x00000000 |
MMC RX TCP Error Frame |
|
GMAC_MMC_RXICMP ERRFRM |
0x0244 |
W |
0x00000000 |
MMC RX ICMP Error Frame |
|
GMAC_MMC_RXIPV4 HDERROCT |
0x0254 |
W |
0x00000000 |
MMC RX OCTET IPV4 Head Error |
|
GMAC_MMC_RXIPV6 HDERROCT |
0x0268 |
W |
0x00000000 |
MMC RX OCTET IPV6 Head Error |
|
GMAC_MMC_RXUDPE RROCT |
0x0274 |
W |
0x00000000 |
MMC RX OCTET UDP Error |
|
GMAC_MMC_RXTCPE RROCT |
0x027c |
W |
0x00000000 |
MMC RX OCTET TCP Error |
|
GMAC_MMC_RXICMP ERROCT |
0x0284 |
W |
0x00000000 |
MMC RX OCTET ICMP Error |
|
GMAC_BUS_MODE |
0x1000 |
W |
0x00020101 |
Bus Mode Register |
|
GMAC_TX_POLL_DE MAND |
0x1004 |
W |
0x00000000 |
Transmit Poll Demand Register |
|
GMAC_RX_POLL_DE MAND |
0x1008 |
W |
0x00000000 |
Receive Poll Demand Register |
|
GMAC_RX_DESC_LIS T_ADDR |
0x100c |
W |
0x00000000 |
Receive Descriptor List Address Register |
|
Name |
Offset |
Size |
Reset Value |
Description |
|
GMAC_TX_DESC_LIS T_ADDR |
0x1010 |
W |
0x00000000 |
Transmit Descriptor List Address Register |
|
GMAC_STATUS |
0x1014 |
W |
0x00000000 |
Status Register |
|
GMAC_OP_MODE |
0x1018 |
W |
0x00000000 |
Operation Mode Register |
|
GMAC_INT_ENA |
0x101c |
W |
0x00000000 |
Interrupt Enable Register |
|
GMAC_OVERFLOW_C NT |
0x1020 |
W |
0x00000000 |
Missed Frame and Buffer Overflow Counter Register |
|
GMAC_REC_INT_WD T_TIMER |
0x1024 |
W |
0x00000000 |
Receive Interrupt Watchdog Timer Register |
|
GMAC_AXI_BUS_MO DE |
0x1028 |
W |
0x00110001 |
AXI Bus Mode Register |
|
GMAC_AXI_STATUS |
0x102c |
W |
0x00000000 |
AXI Status Register |
|
GMAC_CUR_HOST_T X_DESC |
0x1048 |
W |
0x00000000 |
Current Host Transmit Descriptor Register |
|
GMAC_CUR_HOST_R X_DESC |
0x104c |
W |
0x00000000 |
Current Host Receive Descriptor Register |
|
GMAC_CUR_HOST_T X_Buf_ADDR |
0x1050 |
W |
0x00000000 |
Current Host Transmit Buffer Address Register |
|
GMAC_CUR_HOST_R X_BUF_ADDR |
0x1054 |
W |
0x00000000 |
Current Host Receive Buffer Adderss Register |
|
GMAC_HW_FEA_REG |
0x1058 |
W |
0x000d0f17 |
The presence of the optional features/functions of the core |
Only
T-chip
Notes: Size : B - Byte (8 bits) access, HW - Half WORD (16 bits) access, W -WORD (32 bits) access
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